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You searched for: mediatype:texts AND collection:theides AND subject:"RLCG"
[texts]Analytical Delay Model for Distributed On-Chip RLCG Global Interconnects for Different Pole Conditions
Fast delay estimation methods, as compared to simulation techniques, are needed for incremental performance-driven layout synthesis. On-chip inductive and conductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speeds; circuit complexity and interconnect lengths. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity...
Keywords: Moment; Delay calculation; Interconnect; RLCG; VLSI
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